The invention relates in general to digital data processing, especially to digital picture processing, and in particularly to a multi-dimensional parallel storage device having an improved access to stored picture elements which are to be subsequently processed in high-speed data processors.
Due to high computing speeds which are frequently required for processing images, extremely fast computers of specialized design are frequently employed for the digital image processing. Such fast computers require very large storing units for output data, intermediate results and final results of the processing, as well as a very fast access to such storing units, whereby though these requisite access times are still shorter than the access times of available storing elements. In contemporary data-processing units, these contradictory requirements are solved in such a manner that the storage devices are designed with a degree of parallelism.
In parallel storage devices, in a single access cycle for example several storage elements, and hence several storing locations, are addressed simultaneously. Provided that each storage location contains a picture element of an image, then several picture elements are simultaneously available at the output of the arrangement, or vice versa several picture elements are written in simultaneously into the storing arrangement.
The effective time of the cycle, when related to a single picture point or element, is thus reduced by the number of parallel-connected storage elements. In storage devices of this kind, those picture points are with advantage connected in parallel which in the computer are simultaneously required in one processing step, or are presented in the result of a computing step.
There are several forms of such picture segments. These forms of picture segments therefore must also bein agreement with access forms of a parallel storage device. The realization of such access forms requires that the picture points which are to be addressed in parallel be located as different storage elements and, in addition, that the determination of an address pertaining to each of these storage elements be performed with manageable expenditures for arithmetic-logic functional units.
Known are technological solutions which permit the parallel access to all multi-directional lines in a multi-dimensional array. The number of storage elements in such prior-art devices corresponds to a prime number, which in a two-dimensional array is larger than or equal to 5, and in a three-dimensional array is larger than or equal to 11. Such technological solutions are described for example in H. D. Shapiro, Theoretical limitations on the use of parallel memories, Ph. Thesis, December 1975, Report UIUCDSR-75-776, Dep. of Computer Science, University of Illinois, Urbana Ill. and in German Pat. No. 2,718,849.
In digital image processing, in which those groups of picture elements which are to be accessed in parallel and from one access to another are located close to one another, the prior-art arrangements exhibit certain disadvantages. More specifically, these disadvantages reside in the fact that during each access completely new coordinates i, j and k of a window must be applied in the address-computing circuit, and consequently the address computation must be carried out by using large numbers, necessitating the use of words of large width. For relatively small variations of the position of the window in a three-dimensional array, such prior-art arrangements are expensive and relatively slow.
Another disadvantage of such known arrangement is in the fact that parallel access to windows can be made in a straight-line form, whereas in the picture processing also flat and spatial windows are of interest.